Body biasing is a well-known technique of reducing a transistor's leakage current by decoupling the transistor's source from its body and therefore increasing the transistor's turn-on voltage. But when this technique is applied to transistors within the core of an FPGA, special care needs to be taken to provide sufficient discharge paths for the core transistors in case of an electrostatic discharge (ESD) event. A general discussion of the ESD phenomenon and different models of the discharge phenomenon can be found in A. Amerasekera et al., ESD in Silicon Integrated Circuits, 2d ed., Wiley 2002, which is incorporated herein by reference.
Conventionally, a gate-grounded NMOS transistor 100 such as that shown in FIG. 1 is often found in the peripheral region of an FPGA die to provide a discharge path in the case of an ESD event. The NMOS transistor 100 comprises n+ source and drain regions in a p-type substrate and an insulated gate on the substrate. The source, the gate and the substrate are grounded. NMOS transistor 100 contains a parasitic n-p-n bipolar transistor 110 having an emitter that is the source region, a collector that is the drain region and a base that is the substrate. The base/substrate has resistance Rsub. Unlike the NMOS transistor 100, which is a surface device, this n-p-n bipolar transistor 110 is a body device and can therefore handle large currents if turned on through a phenomenon commonly referred to as “snapback conduction”.
Although ESD protection circuits like the one in FIG. 1 may be useful in protecting the die from ESD events happening outside the die according to the human body model (HBM), they are not effective in protecting the die from ESD events occurring inside the die (e.g., at a body-biased transistor according to the charged device model (CDM)). This is, in part, because the resistance of a transmission line between the peripheral ESD circuits and the core of the FGPA is too large, which causes a significant voltage drop along the transmission line. But a simple movement of the ESD protection circuits from the peripheral region into the core could not solve the problem or may even cause new problems. For instance, the ESD protection circuit shown in FIG. 1 requires a large footprint on the die as well as additional components (e.g., a guard ring) to protect adjacent circuitry.
In view of the foregoing, there is a need for ESD protection circuits integrated into the core of an FPGA to protect transistors in the core from internal ESD events.